1. Technical Field
Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the method of manufacturing the capacitor. Example embodiments also relate to a method of manufacturing a capacitor including a lower electrode made of metal and a method of manufacturing a dynamic random access memory device including the capacitor.
2. Description of the Related Art
Semiconductor devices have been widely developed as information devices, e.g., computers. Consequently, semiconductor devices may be required to have a higher operational speeds and larger storage capacities. To meet the above requirements, manufacturing techniques have been developed to improve integration degree, reliability, and response speed.
A capacitor may be employed in a logic device and a memory device (e.g., a dynamic random access memory (DRAM) device) to store data. The capacitor may be formed such that the capacitor has a relatively invariable energy density and relatively stable characteristics independent of voltage. A polysilicon-insulator-polysilicon (PIP) capacitor has been widely used. When a lower electrode of the capacitor is formed using polysilicon, the lower electrode may have a three dimensional shape and may be relatively complex, because polysilicon may be relatively stable at higher temperatures and may have improved step coverage characteristics.
However, a capacitance of the PIP capacitor may be undesirably varied in accordance with a voltage applied to the PIP capacitor. For example, depletion layers may be formed at interfaces between an upper electrode and a dielectric layer and between the upper electrode and an insulating layer when the voltage is applied to the PIP capacitor. Formation of depletion layers may result from the lower electrode and the upper electrode of the PIP capacitor being formed of doped polysilicon. When the depletion layer is formed, a dielectric constant affecting a capacitance of the PIP capacitor may vary as the thickness of the dielectric layer increases. Thus, the capacitance of the PIP capacitor may not be stable. Furthermore, it may be more difficult to obtain a desired capacitance when the PIP capacitor is employed in a higher integrated semiconductor device having a design rule lower than about 90 nm.
To overcome the problem described above, a metal-insulator-metal (MIM) capacitor, including an electrode made of metal, has been developed. In addition, a capacitor including a lower electrode having a cylindrical shape has been developed. To form the cylindrically-shaped lower electrode of the capacitor, a chemical mechanical polishing (CMP) process may be employed for a node separation. However, When a CMP process is employed for the node separation, additional processes for forming a sacrificial layer used as a buffer layer may be required. Consequently, increased efforts and costs may be required to perform the CMP process. Furthermore, where the lower electrode of the capacitor includes a metal, the removal rate of the lower electrode in the CMP process may be lower than where the lower electrode includes polysilicon. Thus, more time may be required to polish a lower electrode including a metal.
As a result, methods have been developed to achieve node separation of the lower electrode without performing the CMP process. Such methods may involve forming a photoresist pattern in an opening used for forming the capacitor. An etching process may be performed for the node separation. However, the above methods may be directed to a concave-shaped lower electrode rather than a cylindrically-shaped lower electrode. A concave-shaped lower electrode may be structurally stable, but the area on which a dielectric layer may be formed may be smaller than the area of a cylindrically-shaped lower electrode. For example, the effective area of a concave-shaped lower electrode may be limited to its inner wall. In addition, the concaved-shaped lower electrodes used in the above methods may include polysilicon instead of metal. As described above, when the lower electrode includes polysilicon, a depletion layer may be formed at an interface between the lower electrode and the dielectric layer. Thus, a dielectric constant affecting the capacitance of the capacitor including the concave-shaped lower electrode may vary as the thickness of the dielectric layer increases such that it may be difficult to obtain the necessary capacitance for a higher integrated semiconductor device.